The present invention relates generally to an integrated circuit package assembly and more particularly to an assembly which includes an Electrostatic Discharge Interposer (hereinafter ESD Interposer) which protects an integrated circuit chip or other such component within the overall assembly from being damaged by ESD or other overvoltage producing conditions.
In the field of integrated circuits, certain architectures have become prominent in semiconductor chips as a result of advantages such as high component density which accompany their use. One such architecture is Metal Oxide Semiconductor (MOS) technology. As with most electronic devices, maximum voltage values to which a particular device may safely be subjected are specified by its manufacturer. MOS technology is no exception. Devices manufactured using MOS and similar technologies utilize a gate structure which includes an insulative thin film layer that is typically formed from silicon dioxide and which is easily damaged by overvoltage conditions. The voltage at which such a layer breaks down is determined by factors such as the dielectric breakdown voltage of the material from which the layer is formed and the actual thickness of the layer within the device. In an unprotected device, the thin film gate insulative layer may suffer from dielectric breakdown at potentials, for example, around 10 volts for a 0.35 micron process whereby the gate is shorted and the device is rendered inoperable.
Unfortunately, however, these devices may also be subjected to the unavoidable and naturally occurring phenomenon of electrostatic discharge (ESD) in many different applications. ESD can easily exceed many thousands of volts which, without protection, can overvoltage virtually any device which includes one or more thin film layers such as those described immediately above whereby to, for example, short the gate of the device and render the device inoperable. In an effort to reduce the problems posed by overvoltage in general and by ESD in particular in these devices, manufacturers have incorporated overvoltage protection on the integrated circuit chip itself, as will be described immediately hereinafter.
Attention is now directed to FIG. 1 which illustrates a prior art integrated circuit package assembly generally indicated by reference numeral 10. Assembly 10 includes a semiconductor die 12 supported on a die attach pad 14 of a lead frame 16. The latter also includes a plurality of electrically conductive lead frame leads 18. Die 12 includes a plurality of ESD protection circuits 20 which are integrally formed with the die. ESD protection circuits 20 are in electrical communication with an overall integrated circuit structure (not shown) which is also integrally formed with the die using standard integrated circuit (IC) techniques. For purposes of simplicity, the specific details of the structure of ESD protection circuits 20 is not illustrated and will not be described herein since such circuitry is well known in the art.
Continuing to refer to FIG. 1, a plurality of bonding wires 22 electrically interconnect lead frame leads 18 with respective ones of ESD protection circuits 20. The assembly is encapsulated using an overall plastic or other such suitable encapsulant material 24. Typically, bonding wires used in integrated circuit assemblies such as those illustrated herein are formed using gold. Hence, these wires are rather expensive. In addition, the bonding wires arguably comprise the most fragile component which makes up an overall IC package assembly. During encapsulation of the assembly, encapsulant material flows around the bonding wires, subjecting the latter to a phenomenon known as wire sweep. Manufacturing costs are increased proportionate to the length of the bonding wires since longer wires are more likely to short to one another or break as a result of wire sweep. For both of the foregoing reasons, it is highly advantageous to minimize the length of these bonding wires.
Still referring to FIG. 1, when an overvoltage condition is applied to one of leads 18 by, for example, an ESD, the voltage is passed to die 12 via one of bonding wires 22. Ideally, the respective ESD protection circuit 20 to which that bonding wire is connected will actively clamp that overvoltage condition in a manner which is well known in the art whereby to shunt the excess voltage to ground to protect the remaining sensitive circuitry of the die from almost certain damage.
While the above described arrangement, which incorporates ESD protection within the die, does provide sensitive elements of the circuitry of the die, such as thin film insulative layers, with protection from overvoltage produced by ESD, the manufacturing difficulties associated with producing this arrangement as well as the limitations of its operational capabilities have become of concern, as will be described immediately hereinafter.
In the manufacture of a typical integrated circuit chip or die, the amount of surface area of silicon which is presently devoted to ESD protection is already of concern. While there is a desire to provide ESD protection, manufacturers are also driven in the highly competitive electronic market place to improve the functionality of a chip while maintaining as small a overall device footprint as possible. Therefore, components such as individual transistors and diodes which are integrally formed within the overall structure of a representative device are produced with the smallest possible geometries so as to conserve the valuable silicon "real estate" of the chip, leaving room for still further components with resultant increases in functionality. Therefore, manufacturers are reluctant to devote still more space to ESD protection at the cost of reduced functionality or a larger device footprint. In fact, it is now estimated that in high component density devices which will incorporate a 0.35 micron fabrication process, the consumption of silicon by ESD structures will approach nearly 50 percent of the available silicon area. Moreover, improved functionality typically results in the need for additional input/output terminals on the chip itself. As the number of input/output terminals increases, still more valuable silicon area must be devoted to ESD protection since each terminal requires protection.
Another concern stems from the desire to provide a device with an adequate level of ESD protection. Typical devices, which are presently available, provide protection from ESD up to approximately 2000 volts which is, in fact, a relatively small discharge. More recently, this level has been seen as inadequate and, in some cases, semi-conductor consumers are demanding more protection. In view of the foregoing discussion, however, manufacturer's ability to provide a significant increase in ESD protection is very limited since, in order to increase protection, the size of the ESD circuitry on the chip must increase dramatically in direct competition with other equally vital component structures integrally formed with the chip.
The present invention resolves the foregoing concerns by providing a highly advantageous ESD Interposer within an overall integrated circuit package assembly which allows for a decrease in chip footprint without affecting chip functionality and further provides protection from ESD at levels well beyond 2000 volts. In one feature of the present invention, bonding wire length may be minimized whereby to reduce manufacturing costs and improve reliability.